Method and system for wafer and device level testing of an integrated circuit

ABSTRACT

A tester comprises test logic and a connector for at least one device under test. The connector, which may comprise a wafer probe for dice on a wafer or a test fixture or either packaged integrated circuit devices or circuit board modules, has connections for the device under test that present an impedance selected to emulate the characteristic impedance of an end-use environment of the device under test. For example, in an embodiment in which the device under test comprises DDR memory and the end-use environment is a DDR memory module, the characteristic impedance is approximately 60 ohms. Thus, the tester of the present invention can accurately simulate operational behavior in an end-use environment of the device under test. Because this accurate simulation is available even for dice on a wafer, the needless expense associated with packaging defective dies and assembling defective dies into modules can be avoided. The test logic, which is couplet to the connector for communication with the device under test, transfers test commands and test data to (tic device under test. The test data and commands are utilized to perform multiple types of tests, including tests of the memory core and internal logic of the device under test. In this manner, the need for multiple types of testers is reduced or eliminated.

BACKGROUND OF THE INVENTION

[0001] 1. Technical Field

[0002] The present invention relates in general to testing electronicdevices and, in particular, to testing integrated circuits. Still moreparticularly, the present invention relates to a method and system forwafer and device-level testing of integrated circuits such as memories.

[0003] 2. Description of the Related Art

[0004] Integrated circuit memories, such as dynamic random accessmemories (DRAMs), are nearly universally utilized to provide datastorage in electronic systems, such as computer systems. To ensureproper operation of the electronic systems, the manufacturing processfor integrated circuit memories includes a number of testing stepsintended to verify that the integrated circuit memories will providereliable performance over the expected lifetime of the electronicsystems in which they are installed.

[0005] A typical manufacturing process for DRAMs begins with thefabrication of a semiconductor wafer containing hundreds or eventhousands of identical dice that each include integrated memorycircuitry. The integrated memory circuitry in each die generallyincludes a memory array for storing data and may include interfacecircuitry for accessing the memory array and performing other operationsin response to memory requests or commands.

[0006] Following wafer fabrication, a quick first pass wafer probe isperformed in an attempt to identify dies on the wafer having defects.The first pass wafer probe, which is conventionally performed utilizingclock, address and data signals having lower than normal operatingfrequencies, writes and reads some or all memory locations to identifydefective rows and columns in the memory array.

[0007] Because memory array defects are not uncommon, a typical DRAM dieis fabricated with one or more redundant rows and columns that can beactivated in place of defective rows and columns by redundancy fusing.Thus, if any defects are detected during the first pass wafer probe,redundancy fusing is performed (e.g., by application of high voltage orlasing) to repair the defects. Once any such redundancy fusing has beenperformed, the wafer is subjected to a second pass wafer probe todetermine the efficacy of fusing in addressing detected defects, and anydies failing the second pass wafer probe are marked as faulty.

[0008] Following the second pass wafer probe, the wafer is scribed intodice. Dice marked as faulty after the wafer probes are discarded, anddice passing the wafer probes are packaged to obtain DRAM devices.Packaging technologies that are commonly used for DRAMs include, amongothers, ball grid array (BGA) and wire bond.

[0009] After packaging, the packaged DRAMs are subjected to device-leveltesting. Device-level testing, like the wafer probe tests, may includelow frequency tests of the DRAM array. Device-level testing may alsoinclude a “burn-in” test in which the packaged DRAMs under test aresubjected to high ambient temperatures and tests of long duration inorder to discover early life failures. Device-level testing also differsfrom wafer probe testing in that, in addition to basic pattern testingof memory arrays, device-level testing generally tests the DC and ACcharacteristics of the packaged DRAMs and the logic and operation of thememory interface. Device-level testing also differs from wafer probetesting in that device-level testing is typically performed at or nearthe rated signal frequencies of the packaged DRAM, which generallyrequires more sophisticated and expensive test equipment.

[0010] Packaged DRAMs that pass the device-level test may subsequentlybe assembled together on circuit cards to form memory modules such asSIMMs (single in-line memory modules) and DIMMs (dual in-line memorymodules). Each memory module is then typically subjected to a final,intensive fault test prior to shipping or installation. The faultsdetected by module testing include faults in the circuit cardsthemselves (e.g., open or shorted traces), faults introduced by moduleassembly (e.g., damaged pin drivers, open or shorted pins, and ESDdamage), and undetected faults in the DRAM circuitry. Followingcompletion of testing, DRAM devices and modules that pass can then beinstalled in an end-use application.

[0011] One drawback of the conventional DRAM manufacturing processoutlined above is that a number of faults are not discovered until latein the manufacturing process, for example, during device-level andmodule testing. As appreciated by the present invention, if such defectscould be detected earlier in the manufacturing process (i.e., duringwafer testing), the significant expense associated with packaging andmodule assembly of the defective dice could be eliminated.Unfortunately, the expense of the sophisticated test equipment currentlyrequired to fully exercise integrated memory circuitry prohibits its useduring wafer testing.

[0012] A second drawback of the conventional manufacturing process isthat several different pieces of specialized test equipment are requiredto fully test many integrated circuits. For example, to test the memoryarray of a DRAM, an algorithmic tester is utilized to write apredetermined data pattern into the memory array, read out the contentsof the memory array, and then compare the output data with the originaldata pattern. A separate vector tester is utilized to exercise thememory's internal test logic, such as that defined in the IEEE 1149.1standard. A third system tester is also employed to verify properoperation of the DRAM in response to commands. As will be appreciated,the use of multiple testers compounds the expense of testing.

[0013] A third drawback of the prior art is that conventional testequipment does not fully emulate the intended end-use environment ofdevices under test. In particular, conventional testers for packagedDRAM devices and modules have a fixed input impedance. This inputimpedance cannot be adjusted and may result in test behavior that isquite different from the operating behavior of the DRAM device undertest when it is eventually installed in an end-use environment.Consequently, there may be an unacceptably high number of faulty devicesor modules that pass the test process and even some satisfactory devicesthat fail the test process.

SUMMARY OF THE INVENTION

[0014] The present invention overcomes the foregoing and additionalshortcomings in the prior art by introducing an improved method andsystem for wafer and device-level testing of integrated circuits such asintegrated circuit memories.

[0015] According to a preferred embodiment of the present invention, atester comprises test logic and a connector for at least one deviceunder test. The connector, which may comprise a wafer probe for dice ona wafer or a test fixture for packaged integrated circuit devices, hasconnections for the device under test that present an impedance selectedto emulate the characteristic impedance of an end-use environment of thedevice under test. For example, in an embodiment in which the deviceunder test comprises DDR memory and the end-use environment is a DDRmemory module, the characteristic impedance is between approximately 54and 66 ohms. Thus, the tester of the present invention can accuratelysimulate operational behavior in an end-use environment of the deviceunder test. Because this accurate simulation is available even for diceon a wafer, the needless expense associated with packaging defectivedies and assembling defective dies into modules can be avoided.

[0016] The test logic, which is coupled to the connector forcommunication with the device under test, transfers test commands andtest data to the device under test. The test data and commands areutilized to perform multiples types of tests, including tests of thecore logic and interface logic of the device under test. In this manner,the need for multiple types of testers is reduced or eliminated.

[0017] Additional objects, features, and advantages of the presentinvention will become apparent from the following detailed writtendescription.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The novel features believed characteristic of the invention areset forth in the appended claims. The invention itself however, as wellas a preferred mode of use, further objects and advantages thereof, willbest be understood by reference to the following detailed description ofan illustrative embodiment when read in conjunction with theaccompanying drawings, wherein:

[0019]FIG. 1 is a high-level block diagram of a memory tester inaccordance with a preferred embodiment of the present invention;

[0020]FIG. 2 is a more detailed block diagram of a tester logic card inthe memory tester illustrated in FIG. 1;

[0021]FIG. 3 depicts a portion of a wafer probe or test fixture forpackaged devices having selectable impedance and propagation delay inaccordance with a preferred embodiment of the present invention;

[0022]FIG. 4 is a high level flowchart of an exemplary test process fortesting DDR memory in accordance with the present invention;

[0023]FIG. 5A is a timing diagram illustrating the timing of the datastrobe (DQS) signals provided to DDR memory under test in relation tothe setup and hold times of WRITE operations to the DDR memory;

[0024]FIG. 5B is a timing diagram depicting the use of a programmabledelay in the data strobe (DQS) signals provided to DDR memory under testto test the timing sensitivity of WRITE operations;

[0025]FIG. 6A is a timing diagram illustrating the timing of data strobe(DQS) signals provided from DDR memory under test in relation to thevalid times for sampling DDR memory output pins during READ operations;

[0026]FIG. 6B is a timing diagram depicting the use of a programmabledelay in the data strobe (DQS) signals provided from DDR memory undertest to test the timing sensitivity of READ operations;

[0027]FIG. 7 illustrates an alternative embodiment of a memory tester inaccordance with the present invention;

[0028]FIG. 8 depicts how variation in the V_(REF) parameter can simulatevariation in the voltage levels of inputs from the tester logic, bothhigh (V_(IH)) and low (V_(IL));

[0029]FIG. 9A illustrates a host system having a memory architecturethat employs a packet bus interface, rather than a conventionalmaster/slave interface;

[0030]FIG. 9B depicts an exemplary memory tester for testing a deviceunder test (DUT) having a packet protocol interface;

[0031]FIG. 9C illustrates an alternative embodiment of a memory testerfor testing a device under test (DUT) having a packet protocolinterface;

[0032]FIG. 10A depicts an exemplary memory tester that employs a shiftregister to permit testing of a memory DUT that supports transfers atmore than twice the clock rate;

[0033]FIG. 10B illustrates an alternative embodiment of a memory testerhaving a memory controller including a shift register that permitstesting of a memory DUT that supports transfers at more than twice theclock rate;

[0034]FIG. 11 depicts a memory tester that utilizes a DDR memorycontroller to test a flash memory DUT having a synchronous memoryinterface; and

[0035]FIG. 12 illustrates a tester architecture having a universaltester logic board and removable DUT control modules to allow testing ofmultiple types of memory DUTs utilizing a single tester logic board.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

[0036] With reference now to the figures and in particular withreference to FIG. 1, there is depicted a high-level block diagram of anillustrative embodiment of a memory tester in accordance with thepresent invention. As illustrated, memory tester 10 includes one or more(e.g., 64) tester logic boards 12 that each includes circuitry fortesting one device under test 14. In the context of the presentinvention, a “device under test” (DUT) is defined as either a die on asemiconductor wafer, a packaged integrated circuit device, or a memorymodule.

[0037] Each tester logic board 12 is coupled to a host 16 and a powersource 18 (e.g., 110 V AC) via a communication bus 20 and a power bus22, respectively. Host 16, which may be a suitably programmed personalcomputer or a control processor, downloads test procedures and testparameters to and receives test results from tester logic boards 12 viacommunication bus 20.

[0038] As further illustrated in FIG. 1, each tester logic board 12 iscoupled to a respective DUT 14 by a controlled impedance connector 24having connection elements suitable for the type of DUT 14 being tested.Thus, if DUTs 14 are memory dice on a wafer, connector 24 comprises awafer probe; if, however, DUTs 14 are packaged memory devices, connector24 comprises a test fixture having sites for connecting to packagedmemory devices. For flexibility, tester logic boards 12 preferablyemploy a “wiuversal” interface that can support either type ofconnectors 24. Importantly, and as discussed further below, theconnection elements of connector 24 present to each DUT 14 acharacteristic impedance that is selected to simulate an end-useenvironment of DUTs 14.

[0039] Referring now to FIG. 2, there is illustrated a more detailedblock diagram of a tester logic board 12 from FIG. 1 in accordance witha preferred embodiment of the present invention. The depicted embodimentincludes circuitry specifically designed for testing DDR dynamic randomaccess memory (DRAM) either on wafer, as packaged devices, or as memorymodules; however, those skilled in the art will appreciate that thepresent invention is not limited to DDR DRAM testing, but is insteadapplicable to testing other types of integrated circuitry. Referencesuseful for an understanding of the depicted embodiment of the presentinvention include the following DDR documentation (which is incorporatedherein by reference):

[0040] a) JEDEC standard No. 21-C: 4.5.10-184 PIN UNBUFFERED DDR SDRAMDIMM FAMILY;

[0041] b) JEDEC standard JESD 79: Double Data Rate (DDR) SDRAMSpecification;

[0042] a) Hyundai Electronics Industries Data Sheet: HYMD1327258-K/H/L32M×72 Unbuffered DDR SDRAM DIMM

[0043] b) Hyundai Electronics Industries Data Sheet: HYMD132G7258-K/H/L32M×72 Registered DDR SDRAM DIMM

[0044] c) Hyundai Electronics Industries Data Sheet: 4Banks×8/4/2M×4/8/16 bits DDR SDRAM

[0045] d) Hyundai Electronics Industries Data Sheet: 128M DDR SDRAM

[0046] e) Micron Technology Design Specification: Revision 0.9, DDRSDRAM Unbuffered DIMM

[0047] j) Micron Technology Data Sheet: 16, 32 AMEG×72 DDR RegisteredSDRAM DIMMs

[0048] g) Micron Technology Data Sheet: MT46V64M4−16 Meg×4×4 banks andMT46V32M8−8 Meg×8×4 banks

[0049] h) Micron Technology Data Sheet: MT46V16M16 Double Data RateSDRAM

[0050] i) NEC Data Sheet: PD45D160442, 45D160842, 45D160164 160 M-bitSynchronous DRAM with Double Data Rate

[0051] j) Fairchild Semiconductor Data Sheet: FMS7857 Phase Locked LoopClock Driver

[0052] k) Fairchild Semiconductor Data Sheet: SSTV16857 14-Bit Registerwith SSTL-2 Compatible J/O and Reset

[0053] l) Fairchild Semiconductor Data Sheet: FM34WO2 2K-Bit JEDECstandard 2-Wire Bus Interface Serial EEPROM

[0054] m) Xilinix Inc. Data Sheet: Virtex™-E 1.8 volt Field ProgrammableGate Arrays;

[0055] n) Xilinix Inc. Data Sheet: Virtex™ 2.5 volt Field ProgrammableGate Arrays;

[0056] o) Xilinix Inc. Application Note: Virtex Series and Spartan-IIFamily: Synthesizable 1.6 GBytes/s DDR SDRAM Controller; and

[0057] p) Intel Data Sheet: Pentium III Processor for the PGA370 Socketat 500 MHz to 1.0B GHz.

[0058] As shown, each tester logic board 12 includes a centralprocessing unit (CPU) 30 that controls the testing performed by thattester logic board 12. CPU 30 receives test procedures, test parameters,test data and expected test results from host 16 via communication bus20 and communication interface 32. Based upon these inputs, CPU 30generates a number of output signals 34-44 (described further below) toorchestrate the operation of the other components of tester logic board12 during testing.

[0059] In addition to CPU 30, tester logic board 12 includes at leastthree principal subsystems: cooling subsystem 48, tester logic 50 andpower subsystem 52. Cooling subsystem 48, which may comprise, forexample, a convection or thermoelectric cooling system, dissipates heatproduced by the components of tester logic board 12. The operation ofcooling subsystem 48 is actively controlled by cooling control signalsgenerated by thermal control logic 56 within tester logic 50 in responseto the output of a thermal sensor 58.

[0060] Power subsystem 52 includes a power supply 70 that utilizes powerreceived from power bus 22 to provide power with the appropriate voltageand current characteristics to CPU 30, communication interface 32, andtester logic 50. Power subsystem 52 further includes a number ofvariable voltage supplies 72-78 that provide voltages utilized tooperate DUT 14. In the illustrated embodiment, in which tester logicboard 12 is designed to test DDR memory, variable power supplies 72-78include variable reference voltage (V_(REF)) supply 72, variable systemtermination voltage (V_(TT)) supply 74, variable V_(DD) supply 76 andvariable V_(DDQ) I/O supply 78. Each of variable voltage sources 72-78outputs a respective selected voltage specified by voltage selectsignals 44 provided by CPU 30.

[0061] Power subsystem 52 finally includes at number of powermeasurement unit (PMUs) 80, which are selectively coupled to the outputpins of DUT 14 by relays 92. Relays 92 can be configured by CPU 30 toroute signals present at the output pins of DUT 14 either to testerlogic 50 for evaluation of the correctness of their logic states and/ortiming or to PMUs 80 for measurement of their DC power characteristics.As described further below, at least one of PMUs 80 measures the sourcevoltage(s) and current supplied to DUT 14 by determining the voltagedrop of V_(DD) across a test resistor 90. Other PMUs 80 preferablymeasure the leakage current of the output pins of DUT 14.

[0062] In addition to the thermal sensor 58 and thermal control logic 56discussed above, tester logic 50 includes a sequencer 100, which maycomprise, for example, a general-purpose processor, a plurality ofbit-slice (e.g., 4-bit) processors working in concert, or anapplication-specific integrated circuit (ASIC). Sequencer 100 is coupledto CPU 30 by a communication interface 102 through which sequencer 100receives test parameters, test data, correct test results, and testprocedures, which are stored by sequencer 100 in random access memory(RAM) 104. Sequencer 100 also receives a reset signal 36 that, whenasserted by CPU 30, causes sequencer 100 to reset itself to a knownstable state by reference to configuration parameters stored withinnon-volatile random access memory (NVRAM) 106. The operation ofsequencer 100 is timed by a clock 108, which may be asynchronous theclocks utilized to operate DUT 14.

[0063] Sequencer 100 is further connected to a DDR memory controller236, which controls DUT 14 through relays 92 and connector 22. Thedepicted arrangement of sequencer 100, DDR memory controller 236,connector 22 and DUT 114 simulates the memory subsystem of a personalcomputer system or other end-use environment of DUT 14. That is,sequencer 100, much like the CPU of a computer system, issues commandsand requests to DDR memory controller 236, which can be implemented as aconventional complementary metal-oxide-semiconductor (CMOS) memorycontroller. Memory controller 236, in turn, communicates with DUT 14 thecommands and requests output by sequencer 100 and correspondingresponses by DUT 14 utilizing conventional CMOS-level signaling. Asshown, DDR memory controller 236 may further be coupled to optional DDRmemory devices 243, which permit test instructions, test data, and/ortest results to be buffered by DDR memory controller 236 before transferto sequencer 100 for storage in RAM 104. Alternate embodiments may boostperformance by using two separate DDR memory controllers, one for DUT 14and one for DDR memory devices 243, or one DDR memory controller with abuffer for write posting.

[0064] During testing, sequencer 100 sets AC test parametrics for DUT14, initiates READ and WRITE data transfers to and from DUT 14, andissues commands for DUT 14 based upon the test information stored in RAM104. In response to receipt of test results from DUT 14, sequencer 100logs the test results in RAM 104 and compares the test results withcorrect results also stored in RAM 104 to make a pass/fail determinationfor DUT 14.

[0065] As further shown in FIG. 2, communication between DDR memorycontroller 236 and DUT 14 is synchronized by timing signals based uponcontroller clocks 120, which are received by DDR memory controller 236.Controller clocks 120 are selected by selector 124 from among aplurality of clock signals generated by clock sources 122 in response toa clock select signal 38 output by CPU 30. The sets of timing signalsutilized to synchronize communication with DUT 14 also include datastrobe signals during READ operations (DQS) included in DQS signals 242generated by DUT 14 and data strobe signals during WRITE operations(DQS) included in DQS signals 244 generated by DDR memory controller236. In order to test the timing sensitivity of DUT 14, DQS signals 242and 244 are among the signals passed through respective sets ofprogrammable delays 238 and 240, which applies a delay specified by arespective one of tester logic (TL) delay signals 40 and DUT delaysignals 42. Delays 238 and 240 each may be implemented, for example,with a Semtech Edge629 delay circuit and associated Semtech Edge693driver circuit.

[0066] With reference now to FIG. 3, a detailed depiction of a preferredembodiment of connector 22 from FIGS. 1 and 2 is given. The illustratedembodiment includes a plurality of sites 150 (only one of which isshown), each of which has connections corresponding to the pinout of aDUT 14. For example, the illustrated DUT 14 is a DDR DRAM devicepackaged in a micro-BGA package having a center-bonded layout of 54 pads152. Accordingly, site 150 has 54 connections 154, each corresponding toa respective one of pads 152. In a preferred embodiment, each connection154 comprises a spring contact, such as a Microspring™ interconnectionelement produced by FormFactor, Inc., of Livermore, Calif.

[0067] Between each connection 154 and DDR memory controller 236, a testimpedance 166 and an optional propagation delay element 168 are coupled.In accordance with an important aspect of the present invention, theinput impedance presented by each connection 154 of site 150, which istest impedance 166, is equivalent to the characteristic impedance of anend-use environment of DUT 14. For example, if the end-use environmentis a DDR memory bus, such as a Dual hi-line Memory Module (DI) or SmallOutline DIMM (SO-DIM), the characteristic impedance is selected to beapproximately 60 Ω, and more particularly, 60 Ω±10 Ω. As shown, in apreferred embodiment, multiple end-use environments can be emulated andnon-standard impedances outside of specified tolerances can be supportedby implementing test impedance 166 as variable impedance. In thispreferred embodiment, a respective selector 160 selects a test impedance166 from among a plurality of different impedances in response to selectsignals 34 provided by CPU 30.

[0068] Optional propagation delay element 168 can be employed to testthe timing sensitivity of DUT 14 to various propagation delays thatresult, for example, from different installation locations of DUT 14 onthe DDR memory bus. As illustrated, the operational effects ofintroducing various different propagation delays into the signal pathbetween connector 154 and DDR memory controller 236 can be testedthrough selection of different trace run lengths by selector 160 ofpropagation delay element 168. As with test impedance 166, selectsignals 34 supplied by CPU 30 control selection of a delay by selector160 of propagation delay element 168. In an alternative embodiment ofthe present invention, the installation of DUT 14 at various locationson the DDR memory bus can be simulated by including within connector 22a series of dummy packaged devices (not illustrated) that can beconnected to the DDR memory bus in a selectable order relative to DUT14. In this manner, testing can simulate the installation of DUT 14 asbeing on the module closest to DDR memory controller 236, second closestto DDR memory controller 236, etc.

[0069] With reference now to FIG. 4, there is illustrated a high-levellogical flowchart of an exemplary process for testing DDR memory, eitheron wafer or in packaged DDR DRAM devices, utilizing tester 10 fromFIG. 1. As illustrated, the process begins at block 180 and thenproceeds to block 182, which depicts tester 12 setting the parametersfor DC parametric tests upon a DUT 14 while DUT 14 is idle. At block184, CPU 30 powers up DUT 14, and, at block 186, causes tester logic 50to measure the DC parametric data of DUT 14. To perform the DCparametric tests, CPU 30 uses unillustrated connections to set relays 92to connect the output pins of DUT 14 to PMUs 80 rather than DDR memorycontroller 236. PMUs 80 then measure the power dissipation of DUT 14 forone or more sets of V_(REF), V_(DD) and V_(DDA) voltages. In addition,PMUs 80 measure the leakage current of the pins of DUT 14. These powerand current measurements are then transferred to sequencer 100 viaunillustrated connections for storage in RAM 104 and comparison withacceptable values to obtain a pass/fail determination at block 190 afterDUT 14 is powered down at block 188. If DUT 14 fails, the processterminates at block 220, which illustrates that DUT 14 is processed as afailing device. If, however, DUT 14 passes, the process loops back toblock 184 until all desired DC test sets are complete, as shown at block192.

[0070] Upon completion of DC testing, the process proceeds from block192 to block 194, which illustrates CPU 30 powering up DUT 14 in testmode. The process proceeds to block 196, which depicts CPU 30 settingthe AC parameters to be utilized during DDR DRAM vector testing. Vectortesting is then performed and the results are stored in RAM 104, asshown at blocks 198-200 and as described in detail below. As representedby decision block 202, DDR DRAM die vector testing (and each of theother AC tests) is preferably performed with multiple different sets ofAC parameters in order to assess the proper operation of DUT 14 over awide range of AC parameters. For DUTs 14 that comprise DDR memory, theAC parameters that can be varied include those summarized below in TableI. Other or additional AC parameters can be tested for different DUTs.TABLE I AC parameter Description T_(CK) Reciprocal of transfer clockfrequency T_(DS) Setup time for DUT (i.e., period defining valid WRITEdata) T_(DH) Hold time for DUT (i.e., period defining valid WRITE data)T_(DQSQ) Time to valid data output (i.e., period defining valid READdata) T_(QH) Output hold time from DQS (i.e., period defining valid READdata) V_(REF) I/O reference voltage that defines midpoint between thelogic low input voltage (V_(IL)) and logic high input voltage (V_(IH))V_(DD) System power supply voltage

[0071] CPU 30 sets the T_(CK) parameter by generating appropriate clockselects 38 to select clock sources 122 of desired frequencies to supplycontroller clocks 120. In a typical testing scenario, it is desirable toselect DUT clock frequencies below, at, and above the rated clockfrequency of DUT 14. For example, for a DDR DRAM DUT 14 having a ratedclock frequency of 333 MHz, it is desirable to performing testing at anumber of transfer clock frequencies ranging from approximately 200 MHZto approximately 366 MHz, which is approximately 333 MHz plus a 10%guard band. In order to test the sensitivity of DUT 14 to the timing ofWRITE operations, CPU 30 sets the T_(DS) and T_(DH) parameters bygenerating DUT delay signals 42 to select the delay applied by delays240 to data strobe DQS and data DQ within signals 244 output to DUT 14by DDR memory controller 236. As illustrated in FIG. 5A, which depictssignal timing without any delay, the midpoint crossing of DQS definesthe midpoint of a transfer of data and provides timing with which dataDQ from DDR memory controller 236 is sampled by DUT 14. The extent ofthe valid period is equal to the sum of a setup time (t_(DS)) prior tothe crossing of the midpoint by strobe DQS during which the data must bevalid and a hold time (t_(DH)) following the crossing of the midpoint bystrobe DQS during which the data must be stable. As shown in FIG. 5B,the sensitivity of DUT 14 to variations in WRITE timing can be tested byapplying separate delays to data strobe DQS and data DQ while DDR memorycontroller 236 supplies appropriate row and column signals for the WRITEoperation. Delays 240 provide a delay to data DQ of length Δt, andprovide a delay to strobe DQS of length Δt₂. Since Δt₂ is greater thanΔt₁, strobe DQS is sent to DUT 14 later than data DQ and initiatessampling beyond the midpoint of the data transfer to DUT 14. By doingso, the hold time (t_(DH)) is effectively decreased by the difference ofΔt₂ minus Δt₁, and the timing sensitivity of DUT 14 can be evaluated. Asa subset of this means, a delay may be applied to either data strobe DQSor data DQ individually.

[0072] CPU 30 similarly tests the timing sensitivity of DUT 14 duringREAD operations by setting the T_(QH) and T_(DQSQ) parameters throughgeneration of TL delay signals 40 that select delays applied by delays238 to the data strobe DQS and data DQ signals in signals 242. Asillustrated in FIG. 6A, which depicts signal timing without any applieddelay, the midpoint crossing of DQS defines the start of the periodduring which data DQ read out of DUT 14 are valid for sampling by DDRmemory controller 236. The extent of the valid period of the READtransfer is equal to the difference of T_(QH) minus T_(DQSQ). As shownin FIG. 6B, the sensitivity of DUT 14 to variations in READ timing canbe tested by applying delays Δt, and Δt₂ to data DQ and data strobe DQS,respectively and the timing sensitivity of DUT 14 can be evaluated.Since Δt₂ is greater than Δt₁, the strobe DQS is sent to DUT 14 laterthan data DQ and initiates sampling by DDR memory controller 236 afterthe start of the data transfer by DUT 14. As a result, the time forDQS-to-DQ skew (t_(DQSQH)) is effectively decreased by the difference ofΔt₂ minus Δt₁, and the timing sensitivity of DUT 14 can be evaluated. Asa subset of this means, delays may be limited to either data strobe DQSor data DQ individually.

[0073] V_(DD) and V_(REF) are set by CPU 30 utilizing voltage selectsignals 44 in order to test DUT 14 for supply voltage margin andreference voltage sensitivity, respectively. Because DUT 14 calibratesV_(IL) and V_(IH) to V_(REF), varying V_(REF) also tests the sensitivityof DUT 14 to various input voltage levels without the need to actuallyvary the voltage levels of the data inputs provided to DUT 14. Therelationship between V_(REF) and apparent V_(IL) and V_(IH) is depictedin FIG. 8.

[0074] Referring again to FIG. 4, after the AC parameters are set atblock 196, CPU 30 downloads vector data and correct test results tosequencer 100, which stores them in RAM 104. Sequencer 100 utilizes thevector data to stimulate appropriate input pins of DUT 14 to exercisethe built-in self-test (BIST) capabilities of DUT 14. In addition,sequencer 100 tests the sensitivity of DUT 14 to the timing of READ andWRITE operations in combination with variable reference voltage V_(REF).Failures caused by combinations of timing parameter changes incombination with sensitivity to input voltage levels induced by V_(REF)variation are discovered by performing successive tests of DUT 14 withdifferent parametric combinations. The probability of failure duringtesting can be increased or decreased by:

[0075] (1) varying test impedance 166 from the characteristic impedanceof the end-use environment in order to affect the amplitude of the DDRmemory bus reflections; and/or

[0076] (2) varying the delay applied by delay element 168 to simulatedifferent locations of DUT 14 on the DDR channel, which affects thetiming of reflections on the DDR memory bus relative to the output ofDUT 14; and/or

[0077] (3) varying V_(REF) either above or below the standard value(e.g., 1.65+0.033V for devices with a nominal V_(DD) of 3.3 V); and/or

[0078] (4) varying delays of one or both of data strobe DQS and data DQ.

[0079] If failure due to combined conditions of impedance, propagationdelays, voltage, and/or timing signal and data delays is observed, CPU30 preferably determines if the failing DUT 14 can pass the test undersimulated work-around conditions. The work-around conditions can besimulated, for example, by applying only certain signal propagation tosimulate restricting the installation locations for DUT 14 along the DDRmemory bus, by varying V_(REF) outside the nominal specified range tosimulate input voltage levels, and by changing the characteristicimpedance to a value outside of the specified ranges for end use systemenvironments. If DUT 14 passes the tests under limited operatingconditions, the failing DUT 14 can be reclassified as passing subject tothe work-around conditions.

[0080] As depicted at block 200, sequencer 100 logs the results of thevector test for subsequent comparison of the test results with thecorrect results to produce a pass/fail determination. As illustrated atblock 202, CPU 30 may then alter the AC parameters and repeat the vectortest utilizing the new AC parameters. If vector testing has beenperformed utilizing each desired set of AC parameters DUT 14 is powereddown, as shown at block 204. If sequencer 100 determines that DUT 14passes the Vector tests, the process proceeds to block 208, which isdescribed below. However, if DUT 14 fails Vector testing and awork-around is not implemented, the process terminates at block 220,where DUT 14 is classified as a failing device.

[0081] Turning now to blocks 208-220, CPU 30 performs DDR memory buscommand testing. As illustrated at block 208, CPU 30 powers up DUT 14.In addition, as depicted at blocks 210-212, CPU 30 downloads a DDRmemory bus command set and correct results to sequencer 100, whichstores them in RAM 104 and then sets initial AC parameters for the testiteration. As shown at block 214, sequencer 100 transfers the DDR memorybus commands to DUT 14, logs responses of DUT 14 to the bus commands ina test log in RAM 104, and compares the responses with the correctresults to make a pass/fail determination. Following block 214, theprocess proceeds to block 216, which represents CPU 30 causing sequencer100 to repeat the DDR memory bus command test for each set of ACparameters.

[0082] As shown at block 218, if DUT 14 fails DDR memory bus commandtesting, the process terminates at block 220 with DUT 14 identified asfailing. However, if DUT 14 passes DDR memory bus command testing, theprocess illustrated in FIG. 4 next proceeds to blocks 222-234, whichdepict data pattern testing. Block 222 shows CPU 30 downloading tosequencer 100 a set of data patterns to be written into and read fromthe memory arrays of DUT 14. Sequencer 100 stores the data patterns inRAM 104. CPU 30 also establishes initial AC parameters for DDR coretesting at block 224.

[0083] As depicted at block 226, sequencer 100 then issues WRITE andREAD operations to DUT 14 to verify operation of the memory arrays ofDUT 14 utilizing the data patterns stored in RAM 104. A typical coretest suite for DUT 14 includes the individual tests summarized below inTable II. TABLE II DDR core test suite tests Description Address ensuresthat all memory array locations can be accessed Data verifies that eachmemory bit operates as both a 1 and a 0 Refresh memory array properlyretains data March algorithms data patterns read out of memory arraymatch those written into memory array Disturb Neighborhood modifyingcontents of a memory cell in Sensitivity Test the memory array does notmodify data (DNST) stored in neighboring memory cells

[0084] Data received from DUT 14 in response to READ accesses arecompared with the expected data pattern by sequencer 100 to make apass/fail determination for DUT 14. As illustrated at block 228, CPU 30may instruct sequencer 100 to perform tests in the DDR core test suiteutilizing a number of additional AC parameter sets.

[0085] After powering down DUT 14 at block 230, sequencer 100 determineswhether DUT 14 passed or failed data pattern testing. Thus, at thetermination of testing, sequencer 100 classifies DUT 14 as passing (asshown at block 234) or failing (as depicted at block 220). Sequencer 100relays the pass/fail determinations to CPU 30, which reports thepass/fail determination for this DUT 14 to host 16.

[0086] Referring now to FIG. 7, there is depicted a high-level blockdiagram of a host-based memory tester 250 in accordance with analternative embodiment of the present invention. In FIG. 7, likereference numerals are utilized to identify elements similar to or thesame as those of the memory tester embodiment illustrated in FIGS. 1-3.

[0087] As shown, memory tester 250 comprises a host 16′ and a testerlogic board 254. Host 16′, which may comprise, for example, aconventional personal computer system or other data processing system,includes a system board 252 having a peripheral interconnect 258 towhich CPU 30 and peripheral adapter 260 are coupled for communication.DDR memory bus 264 couples CPU 30 for communication with DDR memorycontroller 236, which is connected to one or more DDR memory modulesockets 256 mounted on system board 252. Peripheral adapter 260 iscoupled to a storage device 262 that provides non-volatile storage fortest procedures, test parameters, and test data.

[0088] Memory tester 250 employs a host-based tester architecture thatpermits CPU 30 of host 16′ to test a DDR DUT 14 as if DUT 14 weremounted on a standard DDR memory module through the installation, insocket 256, of a tester logic board 254 having an impedance-controlledconnector 22 for DUT 14. Like tester logic board 12 of FIG. 2, testerlogic board 254 includes a cooling subsystem 48 and a power subsystem52, as well as tester logic 50′. In the alternative embodiment shown inFIG. 7, tester logic 50′ is greatly simplified as compared to testerlogic 50 of FIG. 2 in that no sequencer 100 is required and the DDRmemory controller 236 utilized for testing is mounted on system board252. The one major addition to tester logic 50′ is a serial presencedetect (SPD) emulation circuit 255 that identifies tester logic board254 to host 16′ as a DDR memory module upon system reset.

[0089] Information regarding the operation of SPD emulation circuit 255may be found, for example, in JEDEC Standard 21-C SPD Specification,June 2000, which is incorporated herein by reference.

[0090] In operation, memory tester 250 utilizes the test informationstored by storage device 262 (or remotely stored test informationcommunicated via a communication connection) to test DUT 14 according tothe test process depicted in FIG. 4 and described above. The majordifference in the manner in which testing is performed by the embodimentof FIG. 7 is that CPU 30 directly accesses DUT 14 as if DUT 14 weremounted on a DDR memory module installed in socket 256. Thus, forexample, to write to or read from DUT 14, CPU 30 issues an appropriaterequest on DDR memory bus 264, which DDR memory controller 236 passesutilizing CMOS signaling. In response to the request, DDR memorycontroller 236 issues a command to DUT 14 via socket 256 and connector22. Responses by DUT 14 to access commands are returned via the samepath. CPU 30 can then compare the responses provided by DUT 14 withexpected results to male pass/fail determinations for various tests.

[0091] Referring now to FIG. 9A, there is depicted a host system 300that employs an advanced packet protocol memory architecture in lieu ofa conventional master/slave memory interface. In particular, host 300includes a CPU 302 coupled to a packet protocol controller 304. Packetprotocol controller 304, which includes an SDRAM controller 306 and apacket protocol interface 308, communicates 64-bit data packets withpacket protocol system memory 310 via packet protocol bus 305 inresponse to READ and WRITE accesses by CPU 302. As shown, packetprotocol system memory 310 includes conventional DRAM cells, such asSDRAM core 314, as well as a packet protocol interface 312 to supportcommunication over packet protocol bus 305. Utilizing conventionalmemory testing methodologies, a packet protocol system memory deviceunder test would require extremely complex test equipment.

[0092] However, the present invention can greatly simplify testing ofunconventional memory architectures such as that depicted in FIG. 9A.For example, FIG. 9B illustrates an exemplary tester 320 for testing apacket protocol system memory DUT that employs a similar testerarchitecture to the testers illustrated in FIGS. 1, 2 and 7. Inparticular, as indicated by like reference numerals identifying like orcorresponding elements, tester 320 adopts an architecture similar to thehost 300 that represents an end-use environment of packet protocolsystem memory DUT 310′. As shown, tester 320 may utilize a sequencer 322in place of the more complex (and expensive) CPU 302. However, theprincipal differences between host 300 and tester 320 are that tester320 permits the connection of packet protocol system memory DUTs 310′ inthe form of wafer die and packaged devices rather than only modules andthe control of parameters affecting memory access, including voltage,timing delays, bus characteristic impedance, and propagation delays, asdescribed above with respect to FIGS. 1, 2, and 7. 30

[0093]FIG. 9C illustrates an alternative embodiment of a tester 330 fortesting a packet protocol system memory DUT in accordance with thepresent invention. As is apparent by comparison of FIGS. 9C and 9B,tester 330 has much the same construction as tester 320 of FIG. 9B,except for the use of a packet protocol interface 308′ external to SDRAMcontroller 306′. Use of an external packet protocol interface 308′permits extension of the testers shown in FIGS. 1, 2 and 7, which mayincorporate tester logic designed for other memory types, such as DDR,for testing memory devices via a packet protocol bus.

[0094] With reference now to FIGS. 10A and 10B, there are illustratedtwo high level views of a high level memory tester architecture fortesting a memory DUT that supports a transfer frequency greater thantwice the memory clock frequency. For example, in the depictedembodiments, testers 340 and 350, which each include a 64-bit sequencer322, test a 32-bit quad data rate (QDR) SDRAM DUT 346 that supports datatransfers at four times the frequency of memory clock 348. This isachieved by coupling a shift register 344, 344′ between a DDR memorycontroller 342, 342′ and DUT 346 to increase the frequency of datatransfers to and from DUT 346. As shown, shift register 344 can eitherbe external to SDRAM controller 342 as shown in FIG. 10A or integratedwith SDRAM controller 342 to form a QDR SDRAM controller 352 as shown inFIG. 10B. The use of a shift register 344 with a tester as shown inFIGS. 10A and 10B permits extension of the testers shown in FIGS. 1, 2and 7, which may incorporate tester logic designed for other memorytypes such as DDR, for testing memory devices having a data transferfrequency greater than twice the memory clock frequency.

[0095] Referring now to FIG. 11, there is depicted a high level blockdiagram of an exemplary architecture of a memory tester 360 for testinga flash memory DUT 366 having a synchronous DRAM interface. As depicted,memory tester 360 includes a sequencer 362 coupled to a DDR SDRAMcontroller 364, which is in turn coupled to flash memory DUT 366. Byemploying a memory controller having a programmable transfer rate, thememory testers shown in FIGS. 2 and 7 can be adapted to support testingof memory devices (including flash memory) at any multiple of the memoryclock frequency.

[0096] With reference now to FIG. 12, there is illustrated analternative embodiment of a tester 10′ for a testing a plurality ofdiverse DUTs. As above, like and corresponding reference numbers areutilized within FIG. 12 to identify features corresponding to thosewithin tester 10 illustrated in FIG. 1.

[0097] In addition to tester logic boards 12 described in detail above,tester 10′ may have installed therein one or more universal test logicboards 370 containing tester logic that is generic to all memory DUTs.Each universal test logic board 370 is coupled via a standardizedconnector 372 to a DUT-specific tester module 374 containing a memorycontroller, delay circuits, and address hashing hardware specific to oneof a plurality of types of memory DUTs. Tester module 374 is in turncoupled to a DUT 14 b via a DUT-specific test fixture 24 b that providesconnections appropriate to the type and process stage (i.e., wafer,packaged device, or module) of DUT 14 b. Because tester 10′ can berapidly configured for testing any of a plurality of diverse memory DUTssimply by installing the appropriate tester module(s) 374, testing thatformerly required a separate tester for each type of memory device(e.g., DDR, SDRAM, SRAM, Flash and Rambus) can now be performedutilizing a single tester 10′ in accordance with the present invention.

[0098] While the invention has been particularly shown and describedwith reference to a preferred embodiment, it will be understood by thoseskilled in the art that various changes in form and detail may be madetherein without departing from the spirit and scope of the invention.For example, although aspects of the present invention have beendescribed with respect to a tester system executing software thatdirects the functions of the present invention, it should be understoodthat the present invention may alternatively be implemented as a programproduct for use with a data processing system. Programs defining thefunctions of the present invention can be delivered to a data processingsystem via a variety of signal-bearing media, which include, withoutlimitation, non-rewritable storage media (e.g., CD-ROM), rewritablestorage media (e.g., a floppy diskette or hard disk drive), andcommunication media, such as digital and analog networks. It should beunderstood, therefore, that such signal-bearing media, when carrying orencoding computer readable instructions that direct the functions of thepresent invention, represent alternative embodiments of the presentinvention.

What is claimed is:
 1. A tester for testing memory dice on a wafer, saidtester comprising: a wafer probe card having connections for at leastone device under test that comprises a double data rate (DDR) memory dieon a wafer, wherein the connections of the wafer probe card present animpedance selected to emulate the characteristic impedance of an end-useenvironment for a packaged device containing the at least one memorydie; and tester logic, coupled to the wafer probe card, thatcommunicates test data with the device under test via the wafer probecard.
 2. The tester of claim 1, wherein the end-use environment is oneof a DDR memory bus and a DDR memory module and the characteristicimpedance is approximately 60 ohms.
 3. The tester of claim 1, whereinthe connections comprise microsprings.
 4. The tester of claim 1, saidwafer probe card including a variable impedance network having adynamically alterable impedance selected by the tester logic.
 5. Thetester of claim 1, wherein said wafer probe card includes at least onedummy packaged device to simulate operating characteristics of theend-use environment.
 6. The tester of claim 1, wherein the at leastdevice under test includes memory cells, and wherein the tester logicincludes means for communicating voltage signals to device under test toalter which of the memory cells are active for operations to specificaddress locations.
 7. The tester of claim 1, wherein the tester logicincludes a DDR memory controller that interfaces with the wafer probecard.
 8. The tester of claim 1, wherein the tester logic furthercomprises: a clock generator that generates at least one clock signalreceived by the tester logic and at least one timing signal thatcoordinates data transfer between the tester logic and the at least onedevice under test; and one or more delay elements that selectively alterthe relative phases of the at least one clock signal and the at leastone timing signal to test timing sensitivity of the at least one deviceunder test.
 9. The tester of claim 8, wherein during a WRITE operationthe one or more delay elements delay the at least one timing signalreceived by the at least one device under test relative to write data.10. The tester of claim 9, wherein the at least one timing signalreceived by the at least one device under test during the WRITEoperation comprises a data strobe (DQS) signal.
 11. The tester of claim10, wherein the tester logic outputs to the device under test datasignals and row and column signals while the one or more delay elementsdelay the data strobe (DQS) signal to the device under test to testsensitivity of the device under test to input hold and input setuptiming parameters.
 12. The tester of claim 8, wherein during a READoperation the one or more delay elements delay the at least one timingsignal to the tester logic relative to read data received from thedevice under test.
 13. The tester of claim 12, wherein the at least onetiming signal received by the tester logic comprises a data strobe (DQS)signal.
 14. The tester of claim 1, wherein the tester logic furthercomprises: a clock generator that generates at least one clock signalreceived by the tester logic and at least one timing signal thatcoordinates data transfer between the tester logic and the at least onedevice under test; and one or more delay elements that selectively alterthe phase of data signals communicated between the at least one deviceunder test and the tester logic to test timing sensitivity of the atleast one device under test.
 15. The tester of claim 14, wherein the atleast one timing signal is received by the at least one device undertest from the tester logic and comprises a data strobe signal; and saidtester logic includes one or more delay elements that during a WRITEoperation selectively delay data signals received by the at least onedevice under test from the tester logic to test timing sensitivity ofthe at least one device under test for input hold and input setup timingparameters.
 16. The tester of claim 14, wherein the at least one timingsignal is received by the tester logic from the at least one die andcomprises a data strobe signal; and said tester logic includes one ormore delay elements that during a READ operation selectively delay datasignals received by the tester logic from the at least one device undertest to test timing sensitivity of the at least one device under test.17. The tester of claim 8, wherein the one or more delay elements shiftphases of both data signals and the at least one timing signal in smallincrements.
 18. The tester of claim 17, wherein: said tester furthercomprises a power subsystem including a variable reference voltagesupply and variable supply voltage supply coupled to said wafer probecard to supply a reference voltage and a supply voltage to said at leastone device under test through said connections; and said tester logiccomprises means for testing sensitivity of the device under test totiming and voltage combinations by setting the one or more delayelements to delay data strobe and data signals while setting at leastone of the reference voltage and supply voltages outside of normaloperating voltage ranges.
 19. The tester of claim 18, wherein: the waferprobe card comprises at least one variable impedance; and the testerlogic comprises means for varying the variable impedance to testsensitivity of said at least one device under test while testing withmultiple combinations of timing signal and data delays and reference andsupply voltages.
 20. The tester of claim 8, wherein: said tester furthercomprises a power subsystem including a variable reference voltagesupply coupled to said wafer probe card to supply a reference voltage tosaid at least one device under test through said connections; and thetester logic comprises means for varying the reference voltage tosimulate variation of input voltage levels to test sensitivity of saidat least one device under test to input voltage variations.
 21. Thetester of claim 1, wherein said tester logic comprises a tester logicinterface to which a host system communicates memory access requests toaccess the device under test.
 22. The tester of claim 21, and furthercomprising the host system coupled to the tester logic interface,wherein the host system accesses the device under test on the wafer viathe tester logic and wafer probe card by communicating memory accessrequests to the tester logic interface.
 23. A tester for packagedintegrated circuit memory devices, said tester comprising: a testfixture having connections for at least one device under test thatcomprises a packaged integrated circuit double data rate (DDR) memorydevice, wherein the connections of the test fixture present an impedanceselected to emulate the characteristic impedance of an end-useenvironment for the at least one device under test; and tester logic,coupled to the test fixture, that communicates test data with the atleast one packaged memory device via the test fixture.
 24. The tester ofclaim 23, wherein the end-use environment is a DDR memory module and thecharacteristic impedance is approximately 60 ohms.
 25. The tester ofclaim 23, wherein the connections comprise microsprings.
 26. The testerof claim 23, said test fixture including a variable impedance networkhaving a dynamically alterable impedance selected by the tester logic.27. The tester of claim 23, wherein said test fixture includes at leastone dummy packaged integrated circuit device to simulate operatingcharacteristics of the end-use environment.
 28. The tester of claim 23,wherein the tester logic includes a DDR memory controller thatinterfaces with the test fixture.
 29. The tester of claim 23, whereinthe tester logic further comprises: a clock generator that generates atleast one clock signal received by the tester logic and at least onetiming signal that coordinates data transfer between the tester logicand the at least one device under test; and one or more delay elementsthat selectively alter the relative phases of the at least one clocksignal and the at least one timing signal to test timing sensitivity ofthe at least one device under test.
 30. The tester of claim 29, whereinduring a WRITE operation the one or more delay elements delay the atleast one timing signal received by the at least one device under testrelative to write data.
 31. The tester of claim 30, wherein the at leastone timing signal received by the at least one device under test duringthe WRITE operation comprises a data strobe (DQS) signal.
 32. The testerof claim 31, wherein the tester logic outputs to the device under testdata signals and row and column signals while the one or more delayelements delay the data strobe (DQS) signal to the device under test totest sensitivity of the device under test to input hold and input setuptiming parameters.
 33. The tester of claim 30, wherein during a READoperation the one or more delay elements delay the at least one timingsignal to the tester logic relative to read data received from thedevice under test.
 34. The tester of claim 33, wherein the at least onetiming signal received by the tester logic comprises a data strobe (DQS)signal.
 35. The tester of claim 23, wherein the tester logic furthercomprises: a clock generator that generates at least one clock signalreceived by the tester logic and at least one timing signal thatcoordinates data transfer between the tester logic and the at least onedevice under test; and one or more delay elements that selectively alterthe phase of data signals communicated between the at least one deviceunder test and the tester logic to test timing sensitivity of the atleast one device under test.
 36. The tester of claim 35, wherein the atleast one timing signal is received by the at least one device undertest from the tester logic and comprises a data strobe signal; and saidtester logic includes one or more delay elements that during a WRITEoperation selectively delay data signals received by the at least onedevice under test from the tester logic to test timing sensitivity ofthe at least one device under test for input hold and input setup timingparameters.
 37. The tester of claim 35, wherein the at least one timingsignal is received by the tester logic from the at least one die andcomprises a data strobe signal; and said tester logic includes one ormore delay elements that during a READ operation selectively delay datasignals received by the tester logic from the at least one device undertest to test timing sensitivity of the at least one device under test.38. The tester of claim 29, wherein the one or more delay elements shiftphases of both data signals and the at least one timing signal in smallincrements.
 39. The tester of claim 38, wherein: said tester furthercomprises a power subsystem including a variable reference voltagesupply and variable supply voltage supply coupled to said wafer probecard to supply a reference voltage and a supply voltage to said at leastone device under test through said connections; and said tester logiccomprises means for testing sensitivity of the device under test totiming and voltage combinations by setting the one or more delayelements to delay data strobe and data signals while setting at leastone of the reference voltage and supply voltages outside of normaloperating voltage ranges.
 40. The tester of claim 39, wherein: the testfixture comprises at least one variable impedance; and the tester logiccomprises means for varying the variable impedance to test sensitivityof said at least one device under test while testing with multiplecombinations of timing signal and data delays and reference and supplyvoltages.
 41. The tester of claim 29, wherein: said tester furthercomprises a power subsystem including a variable reference voltagesupply coupled to said test fixture to supply a reference voltage tosaid at least one device under test through said connections; and thetester logic comprises means for varying the reference voltage tosimulate variation of input voltage levels to test sensitivity of saidat least one device under test to input voltage variations.
 42. Thetester of claim 23, wherein said tester logic comprises a tester logicinterface to which a host system communicates memory access requests toaccess the device under test.
 43. The tester of claim 42, and furthercomprising the host system coupled to the tester logic interface,wherein the host system accesses the device under test on the wafer viathe tester logic and wafer probe card by communicating memory accessrequests to the tester logic interface.
 44. A tester for memory modules,said tester comprising: a test fixture having collections for at leastone device under test that comprises a double data rate (DDR) memorymodule, wherein the connections of the test fixture present an impedanceselected to emulate the characteristic impedance of an end-useenvironment for the at least one memory module; and tester logic,coupled to the test fixture, that communicates test data with the atleast one device under test via the test fixture.
 45. The tester ofclaim 44, wherein the end-use environment is a host system that employsat least one DDR memory module and the characteristic impedance isapproximately 60 ohms.
 46. The tester of claim 44, wherein theconnections comprise microsprings.
 47. The tester of claim 44, said testfixture including a variable impedance network having a dynamicallyalterable impedance selected by the tester logic.
 48. The tester ofclaim 44, wherein the tester logic includes a DDR memory controller thatinterfaces with the test fixture.
 49. The tester of claim 44, whereinthe tester logic further comprises: a clock generator that generates atleast one clock signal received by the tester logic and at least onetiming signal that coordinates data transfer between the tester logicand the at least one device under test; and one or more delay elementsthat selectively alter the relative phases of the at least one clocksignal and the at least one timing signal to test timing sensitivity ofthe at least one device under test.
 50. The tester of claim 49, whereinduring a WRITE operation the one or more delay elements delay the atleast one timing signal received by the at least one device under testrelative to write data.
 51. The tester of claim 50, wherein the at leastone timing signal received by the at least one device under test duringthe WRITE operation comprises a data strobe (DQS) signal.
 52. The testerof claim 51, wherein the tester logic outputs to the device under testdata signals and row and column signals while the one or more delayelements delay the data strobe (DQS) signal to the device under test totest sensitivity of the device under test to input hold and input setuptiming parameters.
 53. The tester of claim 49, wherein during a READoperation the one or more delay elements delay the at least one timingsignal to the tester logic relative to read data received from thedevice under test.
 54. The tester of claim 53, wherein the at least onetiming signal received by the tester logic comprises a data strobe (DQS)signal.
 55. The tester of claim 44, wherein the tester logic furthercomprises: a clock generator that generates at least one clock signalreceived by the tester logic and at least one timing signal thatcoordinates data transfer between the tester logic and the at least onedevice under test; and one or more delay elements that selectively alterthe phase of data signals communicated between the at least one deviceunder test and the tester logic to test timing sensitivity of the atleast one device under test.
 56. The tester of claim 55, wherein the atleast one timing signal is received by the at least one device tindertest from the tester logic and comprises a data strobe signal; and saidtester logic includes one or more delay elements that during a WRITEoperation selectively delay data signals received by the at least onedevice under test from the tester logic to test timing sensitivity ofthe at least one device under test for input hold and input setup timingparameters.
 57. The tester of claim 55, wherein the at least one timingsignal is received by the tester logic from the at least one die andcomprises a data strobe signal; and said tester logic includes one ormore delay elements that during a READ operation selectively delay datasignals received by the tester logic from the at least one device undertest to test timing sensitivity of the at least one device under test.58. The tester of claim 49, wherein the one or more delay elements shiftphases of both data signals and the at least one timing signal in smallincrements.
 59. The tester of claim 58, wherein: said tester furthercomprises a power subsystem including a variable reference voltagesupply and variable supply voltage supply coupled to said wafer probecard to supply a reference voltage and a supply voltage to said at leastone device under test through said connections; and said tester logiccomprises means for testing sensitivity of the device under test totiming and voltage combinations by setting the one or more delayelements to delay data strobe and data signals while setting at leastone of the reference voltage and supply voltages outside of normaloperating voltage ranges.
 60. The tester of claim 59, wherein: the testfixture comprises at least one variable impedance; and the tester logiccomprises means for varying the variable impedance to test sensitivityof said at least one device under test while testing with multiplecombinations of timing signal and data delays and reference and supplyvoltages.
 61. The tester of claim 44, wherein: the at least one memorymodule comprises a memory device; and the tester logic comprises atester logic interface to which a host system communicates memory accessrequests in order to access the memory device.
 62. The tester of claim61, and further comprising the host system coupled to the tester logicinterface, wherein the host system accesses the memory devices via thetester logic and fixture by communicating memory access requests to thetester logic interface.
 63. A memory tester, comprising: a connectorhaving connections for a double data rate (DDR) memory device under testthat is one of a memory die on a wafer, a packaged integrated circuitmemory device and a memory module, wherein the connections of theconnector present an impedance selected to emulate the characteristicimpedance of an end-use environment for the at least device under test;and tester logic, coupled to the apparatus, that communicates test datawith the device under test.
 64. The memory tester of claim 63, whereinthe end-use environment is one of a DDR memory bus and a DDR memorymodule, and said characteristic impedance is approximately 60 ohms. 65.A method of testing an integrated circuit device, said methodcomprising: connecting to connections of a connector a memory deviceunder test that is one of a double data rate (DDR) packaged integratedcircuit memory device, a DDR memory die on a wafer, and a memory module,wherein the connections present an impedance selected to emulate thecharacteristic impedance of an end-use environment for the device undertest; and coupling test logic to the connector; communicating test databetween the device under test and the test logic via the connector totest the device under test.
 66. A memory tester, comprising: a testfixture having connections for a memory device under test that is one ofa packaged integrated circuit memory device, a memory die on a wafer,and a memory module, wherein the connections present an impedanceselected to emulate the characteristic impedance of an end-useenvironment for the device under test; and: tester logic including: testcircuitry for testing a plurality of types of memory devices; aconnector coupled to said test circuitry to enable connection of atleast one of a plurality of different removable control modules; and aremovable control module coupled to said test circuitry via saidconnector that controls a device under test that is one of saidplurality of types of memory devices.
 67. A memory tester, comprising: atest fixture having connections for at least one device under test thatcomprises one of a memory die on a wafer, a packaged integrated circuitmemory device and a memory module, wherein the connections of the testfixture present an impedance selected to emulate the characteristicimpedance of an end-use environment of the device under test; and testerlogic coupled to the test fixture, said tester logic including a memorycontroller and a packet protocol controller that communicates test databetween the memory controller and the device under test via the testfixture utilizing framed packets.
 68. A memory tester, comprising: atest fixture having connections for at least one device under test thatcomprises one of a memory die on a wafer, a packaged integrated circuitmemory device and a memory module, wherein the connections of the testfixture present an impedance selected to emulate the characteristicimpedance of an end-use environment of the device under test; a clockthat supplies a clock signal to the device under test; and tester logiccoupled to the test fixture, said tester logic including a memorycontroller and a transfer circuit that communicates test data betweenthe memory controller and the device under test via the test fixture atleast twice a frequency of the clock signal.
 69. The memory tester ofclaim 63, and further comprising the memory device under test, whereinthe memory device under test comprises a flash non-volatile memory witha synchronous DRAM-compatible memory interface.